3 Commits

Author	SHA1	Message	Date
ddclark	78255bcca4	Added correct components to voltage regulators	2025-07-28 06:48:32 -07:00
ddclark	81bfa7a222	Added reverse polarity protection to input circuit. Added regulator blocks	2025-07-26 20:30:54 -07:00
ddclark	12cfd8373b	Finished MMDVM sheet ... Synced hierachical connectors Connected sheets on top level added power input sheet added power input circuit	2025-07-20 11:42:16 -07:00