generated from ddclark/Ennnn_NAME_PCBA
Added reverse polarity protection to input circuit. Added regulator blocks
This commit is contained in:
parent
12cfd8373b
commit
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@ -494,71 +494,59 @@
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"wire_width": 6
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},
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{
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"bus_width": 24,
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"bus_width": 20,
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"line_style": 0,
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"name": "+12V",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 0,
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"schematic_color": "rgb(255, 255, 0)",
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"wire_width": 10
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},
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{
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"bus_width": 20,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "+3V3",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 0,
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"schematic_color": "rgb(204, 102, 0)",
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"priority": 2,
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"schematic_color": "rgb(255, 165, 0)",
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"track_width": 0.2,
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"via_diameter": 0.6,
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"via_drill": 0.3,
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"wire_width": 12
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"wire_width": 10
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},
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{
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"bus_width": 24,
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"bus_width": 20,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "+5V",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 1,
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"priority": 3,
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"schematic_color": "rgb(255, 0, 0)",
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"track_width": 0.2,
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"via_diameter": 0.6,
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"via_drill": 0.3,
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"wire_width": 12
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"wire_width": 10
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},
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{
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"bus_width": 24,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 1,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "3V3_SOM",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 2,
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"schematic_color": "rgb(255, 153, 0)",
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"track_width": 0.2,
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"via_diameter": 0.6,
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"via_drill": 0.3,
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"wire_width": 12
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},
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{
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"bus_width": 24,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "GND",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 3,
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"priority": 4,
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"schematic_color": "rgb(0, 0, 0)",
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"track_width": 0.2,
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"via_diameter": 0.6,
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@ -566,40 +554,47 @@
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"wire_width": 12
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},
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{
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"bus_width": 24,
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"bus_width": 16,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "USB",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 4,
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"priority": 5,
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"schematic_color": "rgb(0, 0, 255)",
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"track_width": 0.2,
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"via_diameter": 0.6,
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"via_drill": 0.3,
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"wire_width": 12
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"wire_width": 8
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},
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{
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"bus_width": 34,
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"bus_width": 16,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "VBUS_HUB",
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"name": "VBUS",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 5,
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"schematic_color": "rgb(192, 70, 130)",
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"priority": 6,
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"schematic_color": "rgb(255, 0, 255)",
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"track_width": 0.2,
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"via_diameter": 0.6,
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"via_drill": 0.3,
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"wire_width": 12
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"wire_width": 8
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},
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{
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"bus_width": 24,
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"line_style": 0,
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"name": "VIN",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 1,
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"schematic_color": "rgb(127, 127, 127)",
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"wire_width": 16
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}
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],
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"meta": {
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@ -614,22 +609,18 @@
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"netclass_patterns": [
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{
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"netclass": "+5V",
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"pattern": "+5V"
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"pattern": "*5V*"
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},
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{
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"netclass": "GND",
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"pattern": "GND"
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},
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{
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"netclass": "3V3_SOM",
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"pattern": "+3V3_SOM"
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},
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{
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"netclass": "+3V3",
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"pattern": "+3V3"
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"pattern": "*3V3*"
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},
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{
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"netclass": "VBUS_HUB",
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"netclass": "VBUS",
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"pattern": "*VBUS*"
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},
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{
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@ -639,6 +630,10 @@
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{
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"netclass": "USB",
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"pattern": "*D-"
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},
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{
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"netclass": "VIN",
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"pattern": "*VIN*"
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}
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]
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},
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@ -1031,7 +1026,15 @@
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],
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[
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"f3290b0f-9c87-457c-aef7-93fe8a7a9ecb",
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"POWER_CONDITIONING"
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"POWER"
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],
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[
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"e1af7a2b-c58e-4c52-9c3d-f46f806efa65",
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"REGULATORS"
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],
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[
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"92f9de71-0998-4690-8774-5bc8da605803",
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"REGULATOR_INFO"
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]
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],
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"text_variables": {
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@ -3802,7 +3802,7 @@
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(color 0 0 0 0.0000)
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)
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(uuid "f3290b0f-9c87-457c-aef7-93fe8a7a9ecb")
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(property "Sheetname" "POWER_CONDITIONING"
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(property "Sheetname" "POWER"
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(at 88.9 22.1484 0)
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(effects
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(font
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@ -2645,7 +2645,7 @@
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(uuid "f9cecb34-23e0-4172-895c-60d647fe6915")
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)
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(image
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(at 209.55 87.63)
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(at 209.55 69.85)
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(scale 0.0297229)
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(uuid "0438834f-35ff-4784-bdb8-87d8d8a44ac3")
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(data "iVBORw0KGgoAAAANSUhEUgAABOMAAASOCAYAAACHcuhZAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA"
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@ -43062,7 +43062,7 @@
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)
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)
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(image
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(at 195.58 87.63)
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(at 182.88 69.85)
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(scale 0.0282123)
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(uuid "cd9b1ce5-0d1f-4c2d-8825-ee9bb0530a5f")
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(data "iVBORw0KGgoAAAANSUhEUgAABHsAAASOCAYAAABVDiBEAAAACXBIWXMAAA7EAAAOxAGVKw4bAAAA"
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(dnp no)
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(fields_autoplaced yes)
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(uuid "7152121c-8044-49fd-80fa-ae73ccad7519")
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(property "Reference" "R?"
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(property "Reference" "R13"
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(at 208.28 90.17 90)
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(effects
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(font
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@ -4908,7 +4908,7 @@
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(instances
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(project ""
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(path "/0a39b631-5a77-4664-a8f2-0dd8d62fbc5e/cec39ed2-99af-4908-8ea2-fcb82f236403/dbfc5b4f-a216-4d98-9f87-db3b7d81ee10"
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(reference "R?")
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(reference "R13")
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(unit 1)
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)
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)
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18194
1_Design/SCH/regulator_info.kicad_sch
Normal file
18194
1_Design/SCH/regulator_info.kicad_sch
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35246
1_Design/SCH/regulators.kicad_sch
Normal file
35246
1_Design/SCH/regulators.kicad_sch
Normal file
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