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# How to use the DDCEE KiCAD project template
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## DDCEE KiCAD Library
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- clone the git repo located at https://gitea.clarknm.com/ddclark/KiCAD_DDCEE_Library
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- the repo contains
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-
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| Folder | Use |
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| ------------ | --------------------- |
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| `symbols` | schematic symbols |
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| `footprints` | PCB Footprints |
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| `templates` | Title block templates | |
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- use Preferences -> Configure Paths... to add the folling:
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-
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| Name | Path |
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| ----------------------- | ---------------------------------- |
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| KICAD_DDCEE_LIBRARIES | <path>/KiCAD_DDC_Library |
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| KICAD_USER_TEMPLATE_DIR | <path>/KiCAD_DDC_Library/templates |
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- In the schematic editor use Preferences -> Manage Symbol Libraries... to add
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-
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| Nickname | Library Path | Library Format | | Options | Description |
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| -------- | --------------------------------- | -------------- | --- | ------- | ------------------ |
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| DDCEE | ${KICAD_DDCEE_LIBRARIES}/symbols/ | KiCad | | | DDC Custom Symbols |
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- In the PCB editor use Preferences -> Manage Footprint Libraries... to add
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-
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| Nickname | Library Path | Library Format | | Options | Description |
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| -------- | ----------------------------------- | -------------- | --- | ------- | --------------------- |
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| DDCEE | ${KICAD_DDCEE_LIBRARIES}/footprints | KiCad | | | DDC Custom Footprints |
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### Naming Conventions
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- symbols and footprints will be named with the following convention
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- `TT_<n>P_<fp>_<value>_<mfgr pn>`
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- `TT` - type
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- `n` - number of pins
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- `fp` - footprint
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- `value' - component value
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- `mfgr pn` - manufacturer part number
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## Symbol Types
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Symbol types include but are not limited to:
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| Type Identifier | Comoponent Type |
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| --------------- | -------------------- |
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| IC | Integrated Circuit |
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| CN | Connector |
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| R | Resistor |
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| C | Capacitor |
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| L | Inductor |
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| D | Diode |
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| LED | Light Emitting Diode |
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| FB | Ferrite Bead |
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| LG | Logo |
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| SOM | System on Module |
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| SOC | System on Chip |
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| TP | Test Point |
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| | |
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## Default Fields
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The DDCEE KiCAD symbol library symbol template has the following default fields defined:
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| Field | Use |
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| --------------------------- | --- |
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| Detailed Description | |
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| Manufacturer | |
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| Manufacturer PN | |
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| Supplier 1 | |
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| Supplier 1 PN | |
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| Supplier 1 Link | |
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| Supplier 2 | |
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| Supplier 2 PN | |
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| Supplier 2 Link | |
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| Supplier 3 | |
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| Supplier 3 PN | |
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| Supplier 3 Link | |
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| Assembly instructions | |
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| Alternate Manufacturer 1 | |
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| Alternate Manufacturer 1 PN | |
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| Alternate Manufacturer 2 | |
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| Alternate Manufacturer 2 PN | |
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These fields are in addition to the standard KiCAD symbol fields.
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These fields are also defined in the Pnnnnnn_NAME_PCBA.kicad_sch template file
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# PCBA Project Versioning
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## Background
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A PCBA has four design ouputs that completely define the board. These outputs are
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- Schematic
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- The *schematic* defines all of the components on the bord and how the components are interconnected. This is done in an abstrac way with notional symbols representing components and component connections. The Bill of Material (BoM) is directly tied to the schematic.
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- PCB layout artwork
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- The *layout* defines the physical implementation of the electronic components and their interconnections on a specific board geometry.
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- PCB fabrication diagram
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- The *fabrication diagram* defines the manufacturing board. These parameters can include but are not limited to -
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- Layer stackup (including thickness)
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- Copper weight
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- Materials
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- Solder mask color
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- Testing requirements
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- Controlled impedance requirements
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- PCBA assembly diagram
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- The *assembly diagram* defines specific assembly steps and proceedures. These steps and proceedures can include but are not limited to -
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- Mechanical Parts that need to be installed on the board
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- Coatings
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- Packaging
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- Cuts and jumps
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- ESD handling requirements
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Each of these design outputs should be versioned independently.
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## Rationale
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- Schematic
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- Component values can be changed and pin compatible direct replacement parts can be substituted without affecting the artwork, fabrication, or assembly requirements.
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- PCB Layout artwork
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- Components can be re-arranged on the board and still adhere to the same schematic, fabrication and assembly parameters.
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- If changes in schematic, fabrication, or assembly require a layout change then the layout artwork revision should be incrimented.
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- PCB Fabrication Diagram
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- Fabrication requirements can change without a change in schematic, artwork, or assembly. For instance core materials and thickness can be changed.
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- If changes in schematic, layout artwork, or assembly diagram require changes in the fabrication diagram then the fabrication diagram revision should be incrimented.
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- PCBA Assembly Diagram
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- Assembly requirements can change without a change in schematic, layout artwork, or fabrication diagram. For instance a conformal coating could be added or removed or a wave solder process could be changed to a hand solder process.
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*A change log should be kept for the various design outputs*
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https://keepachangelog.com/en/1.1.0/
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## Part Number Nomenclature
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| Output | Part No | PCB Layer | Revision | Comment |
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| --------------------- | ------- | ----------- | -------- | ------------------------------------- |
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| Schematic | EnnnnS | Silk | Variable | Schematic can be changed without spin |
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| Artwork | EnnnnG | Etch | Fixed | Artwork change requires spin |
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| PCB Fab Diagram | EnnnnF | Solder Mask | Fixed | PCB fab requires spin |
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| PCBA Assembly Diagram | EnnnnA | Silk | Variable | PCBA can be reworked without spin |
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File diff suppressed because it is too large
Load Diff
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"copper_edge_clearance": "error",
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"copper_edge_clearance": "error",
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"copper_sliver": "warning",
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"copper_sliver": "warning",
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"courtyards_overlap": "error",
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"courtyards_overlap": "error",
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"creepage": "error",
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"diff_pair_gap_out_of_range": "error",
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"diff_pair_gap_out_of_range": "error",
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"diff_pair_uncoupled_length_too_long": "error",
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"diff_pair_uncoupled_length_too_long": "error",
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"drill_out_of_range": "error",
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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"extra_footprint": "warning",
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"footprint": "error",
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"footprint": "error",
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"footprint_filters_mismatch": "ignore",
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"footprint_symbol_mismatch": "warning",
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"footprint_symbol_mismatch": "warning",
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"footprint_type_mismatch": "ignore",
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"footprint_type_mismatch": "ignore",
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"hole_clearance": "error",
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"hole_clearance": "error",
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"hole_near_hole": "error",
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"hole_near_hole": "error",
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"hole_to_hole": "error",
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"holes_co_located": "warning",
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"holes_co_located": "warning",
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"invalid_outline": "error",
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"invalid_outline": "error",
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"isolated_copper": "warning",
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"isolated_copper": "warning",
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"lib_footprint_mismatch": "warning",
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"lib_footprint_mismatch": "warning",
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"malformed_courtyard": "error",
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"malformed_courtyard": "error",
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"microvia_drill_out_of_range": "error",
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"microvia_drill_out_of_range": "error",
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"mirrored_text_on_front_layer": "warning",
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"missing_courtyard": "ignore",
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"missing_courtyard": "ignore",
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"missing_footprint": "warning",
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"missing_footprint": "warning",
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"net_conflict": "warning",
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"net_conflict": "warning",
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"nonmirrored_text_on_back_layer": "warning",
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"npth_inside_courtyard": "ignore",
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"npth_inside_courtyard": "ignore",
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"padstack": "warning",
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"padstack": "warning",
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"pth_inside_courtyard": "ignore",
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"pth_inside_courtyard": "ignore",
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"solder_mask_bridge": "error",
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"solder_mask_bridge": "error",
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"starved_thermal": "error",
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"starved_thermal": "error",
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"text_height": "warning",
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"text_height": "warning",
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"text_on_edge_cuts": "error",
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"text_thickness": "warning",
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"text_thickness": "warning",
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"through_hole_pad_without_hole": "error",
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"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
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"too_many_vias": "error",
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"track_angle": "error",
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"track_dangling": "warning",
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"track_dangling": "warning",
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"track_segment_length": "error",
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"track_width": "error",
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"track_width": "error",
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"tracks_crossing": "error",
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"tracks_crossing": "error",
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"unconnected_items": "error",
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"unconnected_items": "error",
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"min_clearance": 0.0,
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"min_clearance": 0.0,
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"min_connection": 0.0,
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"min_connection": 0.0,
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"min_copper_edge_clearance": 0.5,
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"min_copper_edge_clearance": 0.5,
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"min_groove_width": 0.0,
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"min_hole_clearance": 0.25,
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"min_hole_clearance": 0.25,
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"min_hole_to_hole": 0.25,
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"min_hole_to_hole": 0.25,
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"min_microvia_diameter": 0.2,
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"min_microvia_diameter": 0.2,
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},
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},
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"teardrop_options": [
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"teardrop_options": [
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{
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{
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"td_onpadsmd": true,
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"td_onpthpad": true,
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"td_onroundshapesonly": false,
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"td_onroundshapesonly": false,
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"td_onsmdpad": true,
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"td_ontrackend": false,
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"td_ontrackend": false,
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"td_onviapad": true
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"td_onvia": true
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}
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}
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],
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],
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"teardrop_parameters": [
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"teardrop_parameters": [
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"mfg": "",
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"mfg": "",
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"mpn": ""
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"mpn": ""
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},
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},
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"layer_pairs": [],
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"layer_presets": [],
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"layer_presets": [],
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"viewports": []
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"viewports": []
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},
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},
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"duplicate_sheet_names": "error",
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"duplicate_sheet_names": "error",
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"endpoint_off_grid": "warning",
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"endpoint_off_grid": "warning",
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"extra_units": "error",
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"extra_units": "error",
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"footprint_filter": "ignore",
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"footprint_link_issues": "warning",
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"four_way_junction": "ignore",
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"global_label_dangling": "warning",
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"global_label_dangling": "warning",
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"hier_label_mismatch": "error",
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"hier_label_mismatch": "error",
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"label_dangling": "error",
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"label_dangling": "error",
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"label_multiple_wires": "warning",
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"lib_symbol_issues": "warning",
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"lib_symbol_issues": "warning",
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"lib_symbol_mismatch": "warning",
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"missing_bidi_pin": "warning",
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"missing_bidi_pin": "warning",
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"missing_input_pin": "warning",
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"missing_input_pin": "warning",
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"missing_power_pin": "error",
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"missing_power_pin": "error",
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"pin_not_driven": "error",
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"pin_not_driven": "error",
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"pin_to_pin": "warning",
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"pin_to_pin": "warning",
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"power_pin_not_driven": "error",
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"power_pin_not_driven": "error",
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"same_local_global_label": "warning",
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"similar_label_and_power": "warning",
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"similar_labels": "warning",
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"similar_labels": "warning",
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"similar_power": "warning",
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"simulation_model_issue": "ignore",
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"simulation_model_issue": "ignore",
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"single_global_label": "ignore",
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"unannotated": "error",
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"unannotated": "error",
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"unconnected_wire_endpoint": "warning",
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"unit_value_mismatch": "error",
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"unit_value_mismatch": "error",
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"unresolved_variable": "error",
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"unresolved_variable": "error",
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"wire_dangling": "error"
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"wire_dangling": "error"
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}
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}
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},
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},
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"libraries": {
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"libraries": {
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"pinned_footprint_libs": [],
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"pinned_footprint_libs": [
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"DDCEE",
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"CM4"
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],
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"pinned_symbol_libs": [
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"pinned_symbol_libs": [
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"DDCEE"
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"DDCEE"
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]
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]
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},
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},
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"meta": {
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"meta": {
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"filename": "E1001_KG-VRS_Carrier_PCBA.kicad_pro",
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"filename": "E1001_KG-VRS_Carrier_PCBA.kicad_pro",
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"version": 1
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"version": 3
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},
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},
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"net_settings": {
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"net_settings": {
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"classes": [
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"classes": [
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"microvia_drill": 0.1,
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"microvia_drill": 0.1,
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"name": "Default",
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"name": "Default",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 2147483647,
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.2,
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"track_width": 0.2,
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"via_diameter": 0.6,
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"via_diameter": 0.6,
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@ -479,6 +504,7 @@
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"microvia_drill": 0.1,
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"microvia_drill": 0.1,
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"name": "+3V3",
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"name": "+3V3",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 0,
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"schematic_color": "rgb(204, 102, 0)",
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"schematic_color": "rgb(204, 102, 0)",
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"track_width": 0.2,
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"track_width": 0.2,
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"via_diameter": 0.6,
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"via_diameter": 0.6,
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@ -496,6 +522,7 @@
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"microvia_drill": 0.1,
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"microvia_drill": 0.1,
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"name": "+5V",
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"name": "+5V",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 1,
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"schematic_color": "rgb(255, 0, 0)",
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"schematic_color": "rgb(255, 0, 0)",
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"track_width": 0.2,
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"track_width": 0.2,
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"via_diameter": 0.6,
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"via_diameter": 0.6,
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@ -513,6 +540,7 @@
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"microvia_drill": 0.1,
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"microvia_drill": 0.1,
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"name": "3V3_SOM",
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"name": "3V3_SOM",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 2,
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"schematic_color": "rgb(255, 153, 0)",
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"schematic_color": "rgb(255, 153, 0)",
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"track_width": 0.2,
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"track_width": 0.2,
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"via_diameter": 0.6,
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"via_diameter": 0.6,
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@ -530,6 +558,7 @@
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"microvia_drill": 0.1,
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"microvia_drill": 0.1,
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"name": "GND",
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"name": "GND",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 3,
|
||||||
"schematic_color": "rgb(0, 0, 0)",
|
"schematic_color": "rgb(0, 0, 0)",
|
||||||
"track_width": 0.2,
|
"track_width": 0.2,
|
||||||
"via_diameter": 0.6,
|
"via_diameter": 0.6,
|
||||||
@ -547,6 +576,7 @@
|
|||||||
"microvia_drill": 0.1,
|
"microvia_drill": 0.1,
|
||||||
"name": "USB",
|
"name": "USB",
|
||||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"priority": 4,
|
||||||
"schematic_color": "rgb(0, 0, 255)",
|
"schematic_color": "rgb(0, 0, 255)",
|
||||||
"track_width": 0.2,
|
"track_width": 0.2,
|
||||||
"via_diameter": 0.6,
|
"via_diameter": 0.6,
|
||||||
@ -564,6 +594,7 @@
|
|||||||
"microvia_drill": 0.1,
|
"microvia_drill": 0.1,
|
||||||
"name": "VBUS_HUB",
|
"name": "VBUS_HUB",
|
||||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||||
|
"priority": 5,
|
||||||
"schematic_color": "rgb(192, 70, 130)",
|
"schematic_color": "rgb(192, 70, 130)",
|
||||||
"track_width": 0.2,
|
"track_width": 0.2,
|
||||||
"via_diameter": 0.6,
|
"via_diameter": 0.6,
|
||||||
@ -572,11 +603,13 @@
|
|||||||
}
|
}
|
||||||
],
|
],
|
||||||
"meta": {
|
"meta": {
|
||||||
"version": 3
|
"version": 4
|
||||||
},
|
},
|
||||||
"net_colors": null,
|
"net_colors": null,
|
||||||
"netclass_assignments": {
|
"netclass_assignments": {
|
||||||
"/Schematic Top Sheet/USB/VBUS_USB_HUB": "VBUS_HUB"
|
"/Schematic Top Sheet/USB/VBUS_USB_HUB": [
|
||||||
|
"VBUS_HUB"
|
||||||
|
]
|
||||||
},
|
},
|
||||||
"netclass_patterns": [
|
"netclass_patterns": [
|
||||||
{
|
{
|
||||||
@ -617,11 +650,11 @@
|
|||||||
"plot": "2_Fabrication/artwork/",
|
"plot": "2_Fabrication/artwork/",
|
||||||
"pos_files": "",
|
"pos_files": "",
|
||||||
"specctra_dsn": "",
|
"specctra_dsn": "",
|
||||||
"step": "",
|
"step": "E1001_KG-VRS_Carrier_PCBA.step",
|
||||||
"svg": "",
|
"svg": "",
|
||||||
"vrml": ""
|
"vrml": ""
|
||||||
},
|
},
|
||||||
"page_layout_descr_file": "${KICAD_USER_TEMPLATE_DIR}/ddcee_pcb_osh.kicad_wks"
|
"page_layout_descr_file": "kicad-embed://ddcee_pcb_osh.kicad_wks"
|
||||||
},
|
},
|
||||||
"schematic": {
|
"schematic": {
|
||||||
"annotate_start_num": 0,
|
"annotate_start_num": 0,
|
||||||
@ -829,6 +862,7 @@
|
|||||||
],
|
],
|
||||||
"filter_string": "",
|
"filter_string": "",
|
||||||
"group_symbols": true,
|
"group_symbols": true,
|
||||||
|
"include_excluded_from_bom": false,
|
||||||
"name": "",
|
"name": "",
|
||||||
"sort_asc": true,
|
"sort_asc": true,
|
||||||
"sort_field": "${ITEM_NUMBER}"
|
"sort_field": "${ITEM_NUMBER}"
|
||||||
@ -944,6 +978,7 @@
|
|||||||
"net_format_name": "",
|
"net_format_name": "",
|
||||||
"page_layout_descr_file": "${KICAD_USER_TEMPLATE_DIR}/ddcee_sch_osh.kicad_wks",
|
"page_layout_descr_file": "${KICAD_USER_TEMPLATE_DIR}/ddcee_sch_osh.kicad_wks",
|
||||||
"plot_directory": "",
|
"plot_directory": "",
|
||||||
|
"space_save_all_events": true,
|
||||||
"spice_current_sheet_as_root": false,
|
"spice_current_sheet_as_root": false,
|
||||||
"spice_external_command": "spice \"%I\"",
|
"spice_external_command": "spice \"%I\"",
|
||||||
"spice_model_current_sheet_as_root": true,
|
"spice_model_current_sheet_as_root": true,
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
(kicad_sch
|
(kicad_sch
|
||||||
(version 20231120)
|
(version 20250114)
|
||||||
(generator "eeschema")
|
(generator "eeschema")
|
||||||
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||||||
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|
||||||
(paper "USLegal")
|
(paper "USLegal")
|
||||||
(lib_symbols)
|
(lib_symbols)
|
||||||
@ -32,6 +32,10 @@
|
|||||||
(sheet
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|
||||||
(size 12.7 13.97)
|
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|
||||||
|
(exclude_from_sim no)
|
||||||
|
(in_bom yes)
|
||||||
|
(on_board yes)
|
||||||
|
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|
||||||
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|
(fields_autoplaced yes)
|
||||||
(stroke
|
(stroke
|
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|
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|
||||||
@ -70,6 +74,10 @@
|
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(sheet
|
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|
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|
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|
(size 12.7 13.97)
|
||||||
|
(exclude_from_sim no)
|
||||||
|
(in_bom yes)
|
||||||
|
(on_board yes)
|
||||||
|
(dnp no)
|
||||||
(fields_autoplaced yes)
|
(fields_autoplaced yes)
|
||||||
(stroke
|
(stroke
|
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|
(width 0.1524)
|
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@ -110,4 +118,5 @@
|
|||||||
(page "1")
|
(page "1")
|
||||||
)
|
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|
||||||
)
|
)
|
||||||
|
(embedded_fonts no)
|
||||||
)
|
)
|
||||||
|
|||||||
1970814
1_Design/E1001_KG-VRS_Carrier_PCBA.step
Normal file
1970814
1_Design/E1001_KG-VRS_Carrier_PCBA.step
Normal file
File diff suppressed because it is too large
Load Diff
@ -1,7 +1,7 @@
|
|||||||
(kicad_sch
|
(kicad_sch
|
||||||
(version 20231120)
|
(version 20250114)
|
||||||
(generator "eeschema")
|
(generator "eeschema")
|
||||||
(generator_version "8.0")
|
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|
||||||
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|
||||||
(paper "USLegal")
|
(paper "USLegal")
|
||||||
(lib_symbols)
|
(lib_symbols)
|
||||||
|
|||||||
@ -1,14 +1,18 @@
|
|||||||
(kicad_sch
|
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|
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(version 20231120)
|
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|
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|
||||||
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|
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(uuid "5db0d310-b739-442a-b583-6ef7ded0eaed")
|
||||||
(paper "USLegal")
|
(paper "USLegal")
|
||||||
(lib_symbols
|
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|
||||||
(symbol "Connector:TestPoint_Small"
|
(symbol "Connector:TestPoint_Small"
|
||||||
(pin_numbers hide)
|
(pin_numbers
|
||||||
|
(hide yes)
|
||||||
|
)
|
||||||
(pin_names
|
(pin_names
|
||||||
(offset 0.762) hide)
|
(offset 0.762)
|
||||||
|
(hide yes)
|
||||||
|
)
|
||||||
(exclude_from_sim no)
|
(exclude_from_sim no)
|
||||||
(in_bom yes)
|
(in_bom yes)
|
||||||
(on_board yes)
|
(on_board yes)
|
||||||
@ -106,12 +110,17 @@
|
|||||||
)
|
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|
||||||
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|
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|
||||||
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|
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|
||||||
|
(embedded_fonts no)
|
||||||
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|
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|
||||||
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|
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|
||||||
(power)
|
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|
||||||
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|
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|
||||||
|
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|
||||||
|
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|
||||||
(pin_names
|
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|
||||||
(offset 0) hide)
|
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|
||||||
|
(hide yes)
|
||||||
|
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|
||||||
(exclude_from_sim no)
|
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|
||||||
(in_bom yes)
|
(in_bom yes)
|
||||||
(on_board yes)
|
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|
||||||
@ -203,10 +212,15 @@
|
|||||||
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|
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|
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|
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|
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|
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|
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|
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|
||||||
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|
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|
||||||
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|
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|
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|
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|
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|
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|
||||||
|
(hide yes)
|
||||||
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|
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(exclude_from_sim no)
|
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|
||||||
(in_bom yes)
|
(in_bom yes)
|
||||||
(on_board yes)
|
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|
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@ -415,9 +429,9 @@
|
|||||||
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|
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|
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|
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@ -427,9 +441,9 @@
|
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|
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|
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|
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@ -477,6 +491,7 @@
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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@ -556,11 +571,16 @@
|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
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|
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|
||||||
@ -658,12 +678,17 @@
|
|||||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
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|
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|
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(on_board yes)
|
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|
||||||
@ -790,8 +815,83 @@
|
|||||||
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|
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|
||||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
|
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|
||||||
|
(exclude_from_sim no)
|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
||||||
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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@ -918,58 +1018,6 @@
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|
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|
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|
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|
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|
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|
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|
|
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|
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|
|
||||||
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|
|
||||||
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|
|
||||||
(at 33.02 186.69 0)
|
|
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|
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|
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||||||
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|
|
||||||
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|
|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
@ -1043,7 +1159,7 @@
|
|||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
||||||
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@ -1093,7 +1209,7 @@
|
|||||||
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|
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|
||||||
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|
(project "PNnnnnnn_NAME_PCBA"
|
||||||
(path "/0a39b631-5a77-4664-a8f2-0dd8d62fbc5e/cec39ed2-99af-4908-8ea2-fcb82f236403"
|
(path "/0a39b631-5a77-4664-a8f2-0dd8d62fbc5e/cec39ed2-99af-4908-8ea2-fcb82f236403"
|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
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@ -1109,7 +1225,7 @@
|
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|
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|
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|
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|
||||||
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|
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|
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@ -1265,7 +1381,7 @@
|
|||||||
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|
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|
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(project "PNnnnnnn_NAME_PCBA"
|
(project "PNnnnnnn_NAME_PCBA"
|
||||||
(path "/0a39b631-5a77-4664-a8f2-0dd8d62fbc5e/cec39ed2-99af-4908-8ea2-fcb82f236403"
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|
||||||
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|
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|
||||||
(unit 1)
|
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|
||||||
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|
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|
||||||
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|
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|
||||||
@ -1281,7 +1397,7 @@
|
|||||||
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|
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|
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|
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|
||||||
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|
||||||
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|
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|
||||||
(at 63.5 193.04 0)
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|
||||||
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@ -1437,7 +1553,7 @@
|
|||||||
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|
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|
||||||
(project "PNnnnnnn_NAME_PCBA"
|
(project "PNnnnnnn_NAME_PCBA"
|
||||||
(path "/0a39b631-5a77-4664-a8f2-0dd8d62fbc5e/cec39ed2-99af-4908-8ea2-fcb82f236403"
|
(path "/0a39b631-5a77-4664-a8f2-0dd8d62fbc5e/cec39ed2-99af-4908-8ea2-fcb82f236403"
|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
@ -1452,7 +1568,7 @@
|
|||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
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||||||
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|
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|
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|
||||||
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|
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|
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|
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@ -1669,7 +1785,7 @@
|
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|
(property "Reference" "H2"
|
||||||
(at 88.9 185.42 0)
|
(at 88.9 185.42 0)
|
||||||
(effects
|
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|
||||||
(font
|
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@ -1829,7 +1945,7 @@
|
|||||||
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|
(instances
|
||||||
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|
(project "PNnnnnnn_NAME_PCBA"
|
||||||
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|
(path "/0a39b631-5a77-4664-a8f2-0dd8d62fbc5e/cec39ed2-99af-4908-8ea2-fcb82f236403"
|
||||||
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|
(reference "H2")
|
||||||
(unit 1)
|
(unit 1)
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
@ -1845,7 +1961,7 @@
|
|||||||
(dnp no)
|
(dnp no)
|
||||||
(fields_autoplaced yes)
|
(fields_autoplaced yes)
|
||||||
(uuid "63c2dda3-a9d5-4caa-8e88-9ffcba2993ca")
|
(uuid "63c2dda3-a9d5-4caa-8e88-9ffcba2993ca")
|
||||||
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|
(property "Reference" "FID5"
|
||||||
(at 63.5 185.42 0)
|
(at 63.5 185.42 0)
|
||||||
(effects
|
(effects
|
||||||
(font
|
(font
|
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@ -2001,7 +2117,7 @@
|
|||||||
(instances
|
(instances
|
||||||
(project "PNnnnnnn_NAME_PCBA"
|
(project "PNnnnnnn_NAME_PCBA"
|
||||||
(path "/0a39b631-5a77-4664-a8f2-0dd8d62fbc5e/cec39ed2-99af-4908-8ea2-fcb82f236403"
|
(path "/0a39b631-5a77-4664-a8f2-0dd8d62fbc5e/cec39ed2-99af-4908-8ea2-fcb82f236403"
|
||||||
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|
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|
||||||
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|
(unit 1)
|
||||||
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|
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|
||||||
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|
)
|
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@ -2017,7 +2133,7 @@
|
|||||||
(dnp no)
|
(dnp no)
|
||||||
(fields_autoplaced yes)
|
(fields_autoplaced yes)
|
||||||
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|
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|
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|
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|
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@ -2177,7 +2293,7 @@
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|
(project "PNnnnnnn_NAME_PCBA"
|
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|
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|
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|
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|
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(unit 1)
|
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|
||||||
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|
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|
||||||
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|
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|
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@ -2193,7 +2309,7 @@
|
|||||||
(dnp no)
|
(dnp no)
|
||||||
(fields_autoplaced yes)
|
(fields_autoplaced yes)
|
||||||
(uuid "7b3464bb-cb89-49be-8c99-822c93f8966b")
|
(uuid "7b3464bb-cb89-49be-8c99-822c93f8966b")
|
||||||
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|
(property "Reference" "FID3"
|
||||||
(at 50.8 185.42 0)
|
(at 50.8 185.42 0)
|
||||||
(effects
|
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|
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(font
|
(font
|
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@ -2349,7 +2465,7 @@
|
|||||||
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|
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|
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(project "PNnnnnnn_NAME_PCBA"
|
(project "PNnnnnnn_NAME_PCBA"
|
||||||
(path "/0a39b631-5a77-4664-a8f2-0dd8d62fbc5e/cec39ed2-99af-4908-8ea2-fcb82f236403"
|
(path "/0a39b631-5a77-4664-a8f2-0dd8d62fbc5e/cec39ed2-99af-4908-8ea2-fcb82f236403"
|
||||||
(reference "FID?")
|
(reference "FID3")
|
||||||
(unit 1)
|
(unit 1)
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
@ -2365,7 +2481,7 @@
|
|||||||
(dnp no)
|
(dnp no)
|
||||||
(fields_autoplaced yes)
|
(fields_autoplaced yes)
|
||||||
(uuid "94470027-0404-4958-94ff-e6154fd1060f")
|
(uuid "94470027-0404-4958-94ff-e6154fd1060f")
|
||||||
(property "Reference" "TP?"
|
(property "Reference" "TP1"
|
||||||
(at 82.55 190.5 0)
|
(at 82.55 190.5 0)
|
||||||
(effects
|
(effects
|
||||||
(font
|
(font
|
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@ -2525,7 +2641,7 @@
|
|||||||
(instances
|
(instances
|
||||||
(project "PNnnnnnn_NAME_PCBA"
|
(project "PNnnnnnn_NAME_PCBA"
|
||||||
(path "/0a39b631-5a77-4664-a8f2-0dd8d62fbc5e/cec39ed2-99af-4908-8ea2-fcb82f236403"
|
(path "/0a39b631-5a77-4664-a8f2-0dd8d62fbc5e/cec39ed2-99af-4908-8ea2-fcb82f236403"
|
||||||
(reference "TP?")
|
(reference "TP1")
|
||||||
(unit 1)
|
(unit 1)
|
||||||
)
|
)
|
||||||
)
|
)
|
||||||
@ -2541,7 +2657,7 @@
|
|||||||
(dnp no)
|
(dnp no)
|
||||||
(fields_autoplaced yes)
|
(fields_autoplaced yes)
|
||||||
(uuid "b266cc64-0ff3-4b17-ad6d-8d0442d4be7c")
|
(uuid "b266cc64-0ff3-4b17-ad6d-8d0442d4be7c")
|
||||||
(property "Reference" "FID?"
|
(property "Reference" "FID1"
|
||||||
(at 38.1 185.42 0)
|
(at 38.1 185.42 0)
|
||||||
(effects
|
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|
||||||
(font
|
(font
|
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@ -2697,7 +2813,7 @@
|
|||||||
(instances
|
(instances
|
||||||
(project "PNnnnnnn_NAME_PCBA"
|
(project "PNnnnnnn_NAME_PCBA"
|
||||||
(path "/0a39b631-5a77-4664-a8f2-0dd8d62fbc5e/cec39ed2-99af-4908-8ea2-fcb82f236403"
|
(path "/0a39b631-5a77-4664-a8f2-0dd8d62fbc5e/cec39ed2-99af-4908-8ea2-fcb82f236403"
|
||||||
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|
(reference "FID1")
|
||||||
(unit 1)
|
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|
||||||
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|
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|
||||||
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|
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|
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@ -2713,7 +2829,7 @@
|
|||||||
(dnp no)
|
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|
||||||
(fields_autoplaced yes)
|
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|
||||||
(uuid "bcb070d1-ae3e-47cb-956c-d4764a6a5e61")
|
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|
||||||
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|
(property "Reference" "H3"
|
||||||
(at 96.52 185.42 0)
|
(at 96.52 185.42 0)
|
||||||
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|
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|
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|
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@ -2873,7 +2989,7 @@
|
|||||||
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|
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|
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(project "PNnnnnnn_NAME_PCBA"
|
(project "PNnnnnnn_NAME_PCBA"
|
||||||
(path "/0a39b631-5a77-4664-a8f2-0dd8d62fbc5e/cec39ed2-99af-4908-8ea2-fcb82f236403"
|
(path "/0a39b631-5a77-4664-a8f2-0dd8d62fbc5e/cec39ed2-99af-4908-8ea2-fcb82f236403"
|
||||||
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|
(reference "H3")
|
||||||
(unit 1)
|
(unit 1)
|
||||||
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|
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|
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|
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|
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@ -2889,7 +3005,7 @@
|
|||||||
(dnp no)
|
(dnp no)
|
||||||
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|
(fields_autoplaced yes)
|
||||||
(uuid "bedf926e-fa86-422d-8786-94211028658d")
|
(uuid "bedf926e-fa86-422d-8786-94211028658d")
|
||||||
(property "Reference" "#PWR?"
|
(property "Reference" "#PWR062"
|
||||||
(at 110.49 199.39 0)
|
(at 110.49 199.39 0)
|
||||||
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|
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|
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|
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|
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@ -2940,7 +3056,7 @@
|
|||||||
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|
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|
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|
(project "PNnnnnnn_NAME_PCBA"
|
||||||
(path "/0a39b631-5a77-4664-a8f2-0dd8d62fbc5e/cec39ed2-99af-4908-8ea2-fcb82f236403"
|
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|
||||||
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|
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|
||||||
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|
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|
||||||
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|
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|
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|
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|
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@ -2956,7 +3072,7 @@
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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@ -3112,7 +3228,7 @@
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|
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|
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|
||||||
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|
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|
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|
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|
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@ -3128,7 +3244,7 @@
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|
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|
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|
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|
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|
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|
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|
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|
||||||
|
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|
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@ -3335,6 +3455,10 @@
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@ -3364,23 +3488,23 @@
|
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255539
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255539
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Normal file
File diff suppressed because it is too large
Load Diff
222690
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222690
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Normal file
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Load Diff
257
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<mxPoint x="755" y="720" />
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263
6_Documentation/.$block_diagram.drawio.dtmp
Normal file
263
6_Documentation/.$block_diagram.drawio.dtmp
Normal file
@ -0,0 +1,263 @@
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|||||||
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||||||
|
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||||||
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||||||
|
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|
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||||||
|
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||||||
|
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|
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|
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|
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|
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|
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|
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|
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|
<mxGeometry x="10" width="100" height="40" as="geometry" />
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|
<mxCell id="3UlhpxEsc7uBjFAE8jOj-39" value="" style="group" vertex="1" connectable="0" parent="3UlhpxEsc7uBjFAE8jOj-70">
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|
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|
<mxGeometry y="30" width="120" height="240" as="geometry" />
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|
</mxCell>
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|
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|
<mxGeometry x="10" y="260" width="100" height="60" as="geometry" />
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|
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||||||
|
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||||||
|
<mxGeometry x="10" width="100" height="40" as="geometry" />
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|
</mxCell>
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|
<mxCell id="3UlhpxEsc7uBjFAE8jOj-43" value="" style="group" vertex="1" connectable="0" parent="3UlhpxEsc7uBjFAE8jOj-70">
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||||||
|
<mxGeometry x="720" y="740" width="120" height="320" as="geometry" />
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|
</mxCell>
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|
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||||||
|
<mxGeometry y="30" width="120" height="240" as="geometry" />
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|
</mxCell>
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|
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||||||
|
<mxGeometry x="10" y="260" width="100" height="60" as="geometry" />
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||||||
|
</mxCell>
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||||||
|
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||||||
|
<mxGeometry x="10" width="100" height="40" as="geometry" />
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|
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||||||
|
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<mxGeometry relative="1" as="geometry" />
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|
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||||||
|
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||||||
|
<mxGeometry x="490" y="180" width="100" height="60" as="geometry" />
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|
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||||||
|
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|
<mxGeometry relative="1" as="geometry">
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<mxPoint x="940" y="360.3684210526317" as="targetPoint" />
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|
After Width: | Height: | Size: 411 KiB |
Loading…
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Reference in New Issue
Block a user