generated from ddclark/Ennnn_NAME_PCBA
Initial Commit
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c4c7231ee7
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@ -69,16 +69,19 @@
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"copper_edge_clearance": "error",
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"copper_sliver": "warning",
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"courtyards_overlap": "error",
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"creepage": "error",
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"diff_pair_gap_out_of_range": "error",
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"diff_pair_uncoupled_length_too_long": "error",
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"drill_out_of_range": "error",
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"duplicate_footprints": "warning",
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"extra_footprint": "warning",
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"footprint": "error",
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"footprint_filters_mismatch": "ignore",
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"footprint_symbol_mismatch": "warning",
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"footprint_type_mismatch": "ignore",
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"hole_clearance": "error",
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"hole_near_hole": "error",
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"hole_to_hole": "error",
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"holes_co_located": "warning",
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"invalid_outline": "error",
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"isolated_copper": "warning",
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@ -89,9 +92,11 @@
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"lib_footprint_mismatch": "warning",
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"malformed_courtyard": "error",
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"microvia_drill_out_of_range": "error",
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"mirrored_text_on_front_layer": "warning",
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"missing_courtyard": "ignore",
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"missing_footprint": "warning",
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"net_conflict": "warning",
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"nonmirrored_text_on_back_layer": "warning",
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"npth_inside_courtyard": "ignore",
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"padstack": "warning",
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"pth_inside_courtyard": "ignore",
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@ -106,7 +111,9 @@
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"text_thickness": "warning",
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"through_hole_pad_without_hole": "error",
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"too_many_vias": "error",
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"track_angle": "error",
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"track_dangling": "warning",
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"track_segment_length": "error",
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"track_width": "error",
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"tracks_crossing": "error",
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"unconnected_items": "error",
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@ -119,6 +126,7 @@
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"min_clearance": 0.0,
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"min_connection": 0.0,
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"min_copper_edge_clearance": 0.5,
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"min_groove_width": 0.0,
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"min_hole_clearance": 0.25,
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"min_hole_to_hole": 0.25,
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"min_microvia_diameter": 0.2,
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@ -136,10 +144,11 @@
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},
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"teardrop_options": [
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{
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"td_onpadsmd": true,
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"td_onpthpad": true,
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"td_onroundshapesonly": false,
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"td_onsmdpad": true,
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"td_ontrackend": false,
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"td_onviapad": true
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"td_onvia": true
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}
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],
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"teardrop_parameters": [
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@ -221,55 +230,90 @@
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"mfg": "",
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"mpn": ""
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},
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"layer_pairs": [],
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"layer_presets": [
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{
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"activeLayer": -2,
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"layers": [
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3,
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4,
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5,
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6,
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7,
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25,
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33,
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35
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],
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"name": "Assembly Drawings",
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"renderLayers": [
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133,
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134,
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135,
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136,
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137,
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138,
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142,
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144,
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161,
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164,
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165
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]
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},
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{
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"activeLayer": -2,
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"layers": [
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8,
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9,
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10,
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11,
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12,
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19,
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20,
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21,
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25,
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59
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60,
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62
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],
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"name": "Front Assembly",
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"renderLayers": [
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125,
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126,
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127,
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128,
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129,
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133,
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134,
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135,
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@ -495,10 +539,15 @@
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"duplicate_sheet_names": "error",
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"endpoint_off_grid": "warning",
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"extra_units": "error",
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"footprint_filter": "ignore",
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"footprint_link_issues": "warning",
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"four_way_junction": "ignore",
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"global_label_dangling": "warning",
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"hier_label_mismatch": "error",
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"label_dangling": "error",
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"label_multiple_wires": "warning",
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"lib_symbol_issues": "warning",
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"lib_symbol_mismatch": "warning",
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"missing_bidi_pin": "warning",
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"missing_input_pin": "warning",
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"missing_power_pin": "error",
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@ -511,23 +560,30 @@
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"pin_not_driven": "error",
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"pin_to_pin": "warning",
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"power_pin_not_driven": "error",
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"same_local_global_label": "warning",
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"similar_label_and_power": "warning",
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"similar_labels": "warning",
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"similar_power": "warning",
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"simulation_model_issue": "ignore",
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"single_global_label": "ignore",
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"unannotated": "error",
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"unconnected_wire_endpoint": "warning",
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"unit_value_mismatch": "error",
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"unresolved_variable": "error",
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"wire_dangling": "error"
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}
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},
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"libraries": {
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"pinned_footprint_libs": [],
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"pinned_footprint_libs": [
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"DDCEE"
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],
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"pinned_symbol_libs": [
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"DDCEE"
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]
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},
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"meta": {
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"filename": "Ennnn_NAME_PCBA.kicad_pro",
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"version": 1
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"version": 2
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},
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"net_settings": {
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"classes": [
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@ -542,6 +598,7 @@
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"microvia_drill": 0.1,
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"name": "Default",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"priority": 2147483647,
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.2,
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"via_diameter": 0.6,
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@ -550,7 +607,7 @@
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}
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],
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"meta": {
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"version": 3
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"version": 4
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},
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"net_colors": null,
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"netclass_assignments": null,
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@ -776,6 +833,7 @@
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],
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"filter_string": "",
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"group_symbols": true,
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"include_excluded_from_bom": false,
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"name": "",
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"sort_asc": true,
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"sort_field": "${ITEM_NUMBER}"
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@ -891,6 +949,7 @@
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"net_format_name": "",
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"page_layout_descr_file": "${KICAD_USER_TEMPLATE_DIR}/ddcee_sch_osh.kicad_wks",
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"plot_directory": "",
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"space_save_all_events": true,
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"spice_current_sheet_as_root": false,
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"spice_external_command": "spice \"%I\"",
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"spice_model_current_sheet_as_root": true,
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2
1_Design/Ennnn_NAME_PCBA.round-tracks-config
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2
1_Design/Ennnn_NAME_PCBA.round-tracks-config
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@ -0,0 +1,2 @@
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Default True 2.0 3
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False True False
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Load Diff
BIN
4_mCAD/board_outline/pi_hat_board_outline.20241231-190702.FCBak
Normal file
BIN
4_mCAD/board_outline/pi_hat_board_outline.20241231-190702.FCBak
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Binary file not shown.
BIN
4_mCAD/board_outline/pi_hat_board_outline.FCStd
Normal file
BIN
4_mCAD/board_outline/pi_hat_board_outline.FCStd
Normal file
Binary file not shown.
1310
4_mCAD/board_outline/pi_hat_board_outline_cutouts_tht.dxf
Normal file
1310
4_mCAD/board_outline/pi_hat_board_outline_cutouts_tht.dxf
Normal file
File diff suppressed because it is too large
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