Added reverse polarity protection to input circuit. Added regulator blocks

This commit is contained in:
David Clark 2025-07-26 20:30:54 -07:00
parent 12cfd8373b
commit 81bfa7a222
10 changed files with 70000 additions and 987 deletions

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@ -494,71 +494,59 @@
"wire_width": 6 "wire_width": 6
}, },
{ {
"bus_width": 24, "bus_width": 20,
"line_style": 0,
"name": "+12V",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 0,
"schematic_color": "rgb(255, 255, 0)",
"wire_width": 10
},
{
"bus_width": 20,
"clearance": 0.2, "clearance": 0.2,
"diff_pair_gap": 0.25, "diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2, "diff_pair_width": 0.2,
"line_style": 0, "line_style": 0,
"microvia_diameter": 0.3, "microvia_diameter": 0.3,
"microvia_drill": 0.1, "microvia_drill": 0.1,
"name": "+3V3", "name": "+3V3",
"pcb_color": "rgba(0, 0, 0, 0.000)", "pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 0, "priority": 2,
"schematic_color": "rgb(204, 102, 0)", "schematic_color": "rgb(255, 165, 0)",
"track_width": 0.2, "track_width": 0.2,
"via_diameter": 0.6, "via_diameter": 0.6,
"via_drill": 0.3, "via_drill": 0.3,
"wire_width": 12 "wire_width": 10
}, },
{ {
"bus_width": 24, "bus_width": 20,
"clearance": 0.2, "clearance": 0.2,
"diff_pair_gap": 0.25, "diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2, "diff_pair_width": 0.2,
"line_style": 0, "line_style": 0,
"microvia_diameter": 0.3, "microvia_diameter": 0.3,
"microvia_drill": 0.1, "microvia_drill": 0.1,
"name": "+5V", "name": "+5V",
"pcb_color": "rgba(0, 0, 0, 0.000)", "pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 1, "priority": 3,
"schematic_color": "rgb(255, 0, 0)", "schematic_color": "rgb(255, 0, 0)",
"track_width": 0.2, "track_width": 0.2,
"via_diameter": 0.6, "via_diameter": 0.6,
"via_drill": 0.3, "via_drill": 0.3,
"wire_width": 12 "wire_width": 10
}, },
{ {
"bus_width": 24, "bus_width": 24,
"clearance": 0.2, "clearance": 0.2,
"diff_pair_gap": 0.25, "diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 1,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "3V3_SOM",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 2,
"schematic_color": "rgb(255, 153, 0)",
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 12
},
{
"bus_width": 24,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2, "diff_pair_width": 0.2,
"line_style": 0, "line_style": 0,
"microvia_diameter": 0.3, "microvia_diameter": 0.3,
"microvia_drill": 0.1, "microvia_drill": 0.1,
"name": "GND", "name": "GND",
"pcb_color": "rgba(0, 0, 0, 0.000)", "pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 3, "priority": 4,
"schematic_color": "rgb(0, 0, 0)", "schematic_color": "rgb(0, 0, 0)",
"track_width": 0.2, "track_width": 0.2,
"via_diameter": 0.6, "via_diameter": 0.6,
@ -566,40 +554,47 @@
"wire_width": 12 "wire_width": 12
}, },
{ {
"bus_width": 24, "bus_width": 16,
"clearance": 0.2, "clearance": 0.2,
"diff_pair_gap": 0.25, "diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2, "diff_pair_width": 0.2,
"line_style": 0, "line_style": 0,
"microvia_diameter": 0.3, "microvia_diameter": 0.3,
"microvia_drill": 0.1, "microvia_drill": 0.1,
"name": "USB", "name": "USB",
"pcb_color": "rgba(0, 0, 0, 0.000)", "pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 4, "priority": 5,
"schematic_color": "rgb(0, 0, 255)", "schematic_color": "rgb(0, 0, 255)",
"track_width": 0.2, "track_width": 0.2,
"via_diameter": 0.6, "via_diameter": 0.6,
"via_drill": 0.3, "via_drill": 0.3,
"wire_width": 12 "wire_width": 8
}, },
{ {
"bus_width": 34, "bus_width": 16,
"clearance": 0.2, "clearance": 0.2,
"diff_pair_gap": 0.25, "diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2, "diff_pair_width": 0.2,
"line_style": 0, "line_style": 0,
"microvia_diameter": 0.3, "microvia_diameter": 0.3,
"microvia_drill": 0.1, "microvia_drill": 0.1,
"name": "VBUS_HUB", "name": "VBUS",
"pcb_color": "rgba(0, 0, 0, 0.000)", "pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 5, "priority": 6,
"schematic_color": "rgb(192, 70, 130)", "schematic_color": "rgb(255, 0, 255)",
"track_width": 0.2, "track_width": 0.2,
"via_diameter": 0.6, "via_diameter": 0.6,
"via_drill": 0.3, "via_drill": 0.3,
"wire_width": 12 "wire_width": 8
},
{
"bus_width": 24,
"line_style": 0,
"name": "VIN",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 1,
"schematic_color": "rgb(127, 127, 127)",
"wire_width": 16
} }
], ],
"meta": { "meta": {
@ -614,22 +609,18 @@
"netclass_patterns": [ "netclass_patterns": [
{ {
"netclass": "+5V", "netclass": "+5V",
"pattern": "+5V" "pattern": "*5V*"
}, },
{ {
"netclass": "GND", "netclass": "GND",
"pattern": "GND" "pattern": "GND"
}, },
{
"netclass": "3V3_SOM",
"pattern": "+3V3_SOM"
},
{ {
"netclass": "+3V3", "netclass": "+3V3",
"pattern": "+3V3" "pattern": "*3V3*"
}, },
{ {
"netclass": "VBUS_HUB", "netclass": "VBUS",
"pattern": "*VBUS*" "pattern": "*VBUS*"
}, },
{ {
@ -639,6 +630,10 @@
{ {
"netclass": "USB", "netclass": "USB",
"pattern": "*D-" "pattern": "*D-"
},
{
"netclass": "VIN",
"pattern": "*VIN*"
} }
] ]
}, },
@ -1031,7 +1026,15 @@
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],
[
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"REGULATOR_INFO"
] ]
], ],
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